pkoduct desckiption the ad565 is a fast 12-bit digital-to-analog converter combined with a high stability voltage reference on a single monolithic chip. the ad565 chip uses 12 precision, high speed bipolar cur- rent steering switches, control amplifier, laser-trimmed thin film resistor network, and buried zener voltage reference to pro- duce a very fast, high accuracy analog output current. the combination of performance and flexibility in the ad565 has resulted from major innovations in circuit design, an im- portant new high-speed bipolar process, and continuing ad- vances in laser-wafer-trimming techniques (lwt). the ad565 has a 10 -. 90% full scale transition time under 35 nanoseconds and settles to within :t1/2lsb in 200 nanoseconds. ad565 chips are laser-trimmed at the wafer level to ::t1/8lsb typical linearity and are specified to :t1/4lsb max error (k and t grades) at +25c. this high speed and accuracy make the ad565 the ideal choice for high speed display drivers as well as fast analog-to-digital converters. the subsurface (buried) zener diode on the chip provides a low-noise voltage reference which has long-term stability and temperature drift characteristics comparable to the best dis- crete reference diodcs. the laser trimming process which pro- vides the excellent linearity is also used to trim both the abso- lute value of the refercnce as well as its temperaturc coefficient. the ad565 is thus well suited for wide temperature rangc performance with maximum linearity error ::t1/2lsb and guaranteed monotonicity over the full temperature range. typical full scale gain t.c. is 10ppm/c. the ad 56 5 is available in four performance grades and two package types. the ad565j and k are specified for use over the 0 to 70c temperature range and arc both available in either a 24-pin, hermetically-sealed, side-brazed ceramic dip, or a 24 pin plastic dip. the ad565s and t grades are specified for the -55 c to + 12 5 c range and are available in the ceramic package. .covered by patent numbers: 3,803,590; 3,890,611; 3,932,863; 3,978,473; 4,020,486; and other patents pending. analog devices old complete high speed 12-bit monolithic 0/ a converter features single chip construction very high speed: settles to 1/2lsb in 200ns full scale switching time: 30ns high stability buried zener reference on chip monotonicity guaranteed over temperature linearity guaranteed over temperature: 1/2lsb max (ad565k, t) low power: 225mw including reference pin-out compatible with ad563 low cost ($16.00 in 100's ad565jn) "- i ) --- -- '.",.- ,..,..,..."'" /. a ' ' d """' 5 '." 6 """' 5 ~jli . i~.!(}'~'f~1~~f*~~~:'~~!t . "t~,.. .c.yt-,. ,"\",,~.~,:8 p!?odljrt highlights 1. the ad565 is a self-contained current output dac and voltage reference fabricated on a single 1c chip. 2. the device incorporates a newly developed. fu lly differen- tial, non-saturating precision current switching cell structure which combines the dc accuracy and stability first developed in the ad562 with very fast switching times and an opti- mally-damped settling characteristic. 3. the internal buried zener reference is laser-trimmed to 10.00 volts with a :t1 % maximum error. the reference volt- age is available externally and can supply up to 1. 5ma beyond that required for the reference and bipolar offset resistors. 4. the chip also contains sicr thin film application resistors which can be used either with an external op amp to pro- vide a precision voltage output or as input resistors for a successive approximation aid converter. the resistors are matched to the internal ladder network to guarantee a low gain temperature coefficient and are laser-trimmed for mini- mum full scale and bipolar offset errors. 5. the pin-out of the ad565 is compatible with the industry- standard ad563 so that a system can easily be upgraded to higher speed performance without board changes. 6. the single-chip construction makes the ad 56 5 inherently more reliable than hybrid multi-chip designs. the ad565s and t grades with guaranteed linearity and monotonicity over the -55 c to + 125" c range are especially recommended for high reliability needs in harsh environments. these units are available fully processed to mil-std-883, level b. obsolete
specifications (ta =+25c, vcc = +15v, vee = -15v, unless otherwise specified) vcc. +13.5 to +16.5v dc vee._-13.5_.to_~j_6c.?ov dc power supply gain sensitivity vcc = +15v. :tl0% vel: = -15v. :t10% programmable output range (see figures 4.5,6) '--_u ' m external ad] ustments gain error with fixed 50sl resistor for r2 (fig. 4) bipolar zero error with fixed 50sl resistor for rl (fig. 5) gain adjustment range (fig. 4) bipolar zero adjustment range reference input input impedance reference output voltage current (available for external loads) 3 -12 3 -12 5 -18 ' --- 3 is 3 15 10 25 0 to +5 -2.5 to +2.5 oto+l0 -5 to +5 -10 to +10 0 to +5 -2.5 to +2.5 0 to + 10 -5 to +5 -10 to +10 . "-- . :to. 1 :to.25 :to.05 :to.15 :to.25 :to.15 15k 20k 25k 9.90 10.00 10.10 1.5 2.5 y--- power dissipation ---ni 3~ specificatio", ,object (0 change without notice, 4 4 5 -18 ma ma 10 25 ppm of f.s/% ppm of f.s/% v v v v v :to.25 % of f.s. :to. 1 % of f.s. % of f.s. % of f.s. 25k ~ sl 10.10 v ma 345 l m'j! ..-. . " ad565] ad565k model min typ max min typ max units '. - data inputs (pins 13 to 24) ttl or 5 volt cmos (tmin to tmax) input voltage bit on logic "1" +2.0 +5.5 +2.0 +5.5 v bit off logic "0" +0.8 +0.8 v logic current (each bit) bit on logic "1" +120 +300 +120 +300 jla bit off logic "0" +35 +100 +35 +100 jla resolution 12 12 bits output current unipolar (all bits on) -1.6 -2.0 -2.4 -1.6 -2.0 -2.4 ma bipolar (all bits on or off) :to. 8 :t1.0 :t1.2 :to.8 :t1.0 :t1.2 ma resistance (exclusive of span resistors) 6k 8k iok 6k 8k 10k n offset unipolar 0.01 0.05 0.01 0.05 % of f.s. bipolar (figure 5. r2 = 50n fixed) 0.05 0.15 0.05 0.1 % of f.s. capacitance 25 25 pf compliance voltage tmin totmax -1.5 +10 -1.5 +10 v accuracy (error relative to full scale) +25c :tl/4 :tl/2 :t1/8 :t1/4 lsb (0.006) (0.012) (0.003) (0.006) % of f.s. tmin to tmax :t1/2 :t3/4 :tl/4 :tl/2 lsb (0.012) (0.018) (0.006) (0.012) % of f.s. differential nonlinearity +25c :tl/2 :t3/4 :tl/4 :tl/2 lsb tmin to t max monotonicity guaranteed monotonicity guaranteed temperature coefficients with internal reference unipolar zero 1 2 1 2 ppm/oc bipolar zero 5 10 5 10 ppm/oc gain (full scale) 15 30 10 20 ppmtc differential nonlinearity 2 2 ppmtc settling time to l/2lsb all bits on-to-off or off-to-on 200 400 200 400 ns full scale transition 10% to 90% delay plus rise time 15 30 15 30 ns 90% to 10% delay plus fall time 30 50 30 50 ns temperature range operating 0 +70 0 +70 c storage (0 package) -65 +150 -65 +150 vc storage (n package) -25 +100 -25 +100 c power requirements i :to.l :to.05 :to.25 :to. 15 15k 20k 9.90 10.00 1.5 2.5 ---- 225 -7- obsolete
+25"c 1/2 3/4 :tl/4 112 lsb ad565s ad56st model min typ max min typ max units data inputs (pins 13 to 24) til or 5 volt cmos (tmin to tmax) input voltage bit on logic "i" +2.0 +5.5 +2.0 +5.5 v bit off logic "0" +0.8 +0.8 v logic current (each bit) bit on logic "i" +120 +300 +120 +300 1j.a bit off logic "0" +35 +100 +35 +100 1j.a resolution 12 12 bits output current unipolar (all bits on) -1.6 -2.0 -2.4 -1.6 -2.0 -2.4 ma bipolar.(all bits on or off) :to.8 :t1.0 :t1.2 :to.8 :t1.0 :t1.2 ma resistance (exclusive of span resistors) 6k 8k iok 6k 8k 10k n offset unipolar 0.01 0.05 0.01 0.05 % of f.s. bipolar (figure 5, r2 = son fixed) 0.05 0.15 0.05 0.1 % of f .s. capacitance 25 25 pf compliance voltage t mill to t max -1.5 +10 -1.5 +10 v accuracy (error relative to full scale) +25 c :t1/4 :t112 :!:1/8 :t1/4 lsb (0.006) (0.012) (0.003) (0.006) % of f.s. tmin to tmax :tl/2 :t3/4 :!:1/4 :t112 lsb (0.012) (0.018) (0.006) (0.012) % of f.s. differential nonlinearity +25c :t1/2 :t3/4 :t1/4 :t1l2 lsb tmin to tmax monotonicity guaranteed monotonicity guaranteed temperature coefficients with internal reference unipolar zero i 2 i 2 ppm/c bipolar zero 5 10 5 10 ppm/oc gain (full scale) is 30 10 15 ppm/c differential nonlinearity 2 2 ppm/c settling time to 1/2lsb all bits on-to-0ff or off-to-0n 200 400 200 400 ns full scale transition 10% to 90% delay plus rise time is 30 is 30 ns 90% to 10% delay plus fall time 30 50 30 50 ns temperature range operating -55 +125 -55 +125 c storage (d package) -65 +150 -65 +150 c .---- --- power requirements vcc, +13.5 to +16.5v de 3 5 3 5 ma vee, -13.5 to -16.5v de -12 -18 -12 -18 ma .-.. ---.- ..--.--- n__- - power supply gain sensitivity vcc = +15v, :t1o% 3 10 3 10 ppm of f.s.i% vee = -15v, :t1o% 15 25 15 25 ppm of f.s.i% programmable output range (see figures 4.5,6) 0 to +5 0 to +5 v -2.5 to +2.5 -2.5 to +2.5 v oto+l0 oto+l0 v -5 to +5 -5 to +5 v -10 to +10 -10 to +10 v external adjustments gain error with fixed son resistor for r2 (fig. 4) :to. i :to.25 :to. i :to.25 % of f .5. bip'olar zero error with fixed son resistor for r 1 (fig. 5) :to.05 :to.15 i :to.05 :to. 1 i % of f.s. gain adjustment range (fig. 4) :to.25 :to.25 % of f .5. bipolar zero adjustment range :to. 15 :to. 15 % of f.s. reference input input impedance 15k 20k 25k i 15k 20k 25k ' q reference output --i- ._--- voltage 9.90 10.00 10.10 i 9.90 10.00 10.10 v current (available for external loads) 1.5 2.5 1.5 2.5 ma --'-- --- power dissipation 225 345 225 345 mw . specifications subject to change without notice. ... obsolete
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